a) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a lower gate (so-called staggered gate or under-gated)type MOS thin film transistor having a gate electrode under the channel region.
b) Description of the Related Art
A conventional method of manufacturing a lower gate type MOS thin film transistor is known as illustrated in FIG. 8. With this method, on an insulating film 12 covering the surface of a semiconductor substrate 10, a gate electrode layer 14, a gate insulating layer 16, and a semiconductor layer 18 such as polycrystalline silicon are sequentially formed. Using a resist layer 20 as a mask, impurity ions such as BF2 are injected selectively in the semiconductor layer 18 to form a source region 18S and a drain region 18D.
For such a thin film transistor, it is important to precisely control the offset amount S of the drain region 18D from the gate electrode layer 14. If the offset amount S is small (or no offset), an off-current (leakage current) becomes great, whereas if the offset amount S is large, an on-current becomes less (or no on-current). The offset amount S is generally set to a predetermined value within the range of about 0.3 to 0.6 .mu.m.
With the conventional method, however, an alignment error in the order of 0.3 to 0.4 .mu.m is likely to occur under the condition that the ion injection process for the source and drain regions is performed by using the resist layer 20 as the mask. Therefore, the drain and source regions are formed at many different positions in a single manufacturing lot. The difference of the position of a drain region changes the offset amount S and transistor characteristics.